1. Field of the Invention
The present invention relates to a semiconductor integrated circuit designed by a master-slice technique, and more particularly to an improvement of arrangement transistor elements for simplified wirings.
2. Description of the Related Art
Among C-MOS integrated circuits designed by the master-slice technique, so-called gate-array devices have a matrix of cells made of at least one N-channel MOS FET and at least one P-channel MOS FET on a semiconductor wafer and is formed by wiring the cells to realize a required circuit operation. Since those gate-array devices have features of short period of time required for design and manufacture, they are widely used and studied (for example, Japanese Published Unexamined Patent Application No. 60-145642).
The gate-array devices have a semiconductor chip having such a cell-arrangement that a plurality of basic cells are arrayed in rows and columns in the central portion which is surrounded by a plurality of input/output (I/O) cells disposed in the peripheral portion. More specifically, each of the basic cells in C-MOS gate-array devices includes typically two N-channel MOS FET's and typically two P-channel MOS FET's. The N-channel MOS FET's in each basic cell have an arrangement of a drain region, a gate electrode, a source region, another gate electrode and another drain region in this order in parallel with the row direction. The N-channel MOS FET's in other basic cells in the same row are disposed side by side. The P-channel MOS FET's in each basic cell are disposed at a portion adjacent to the corresponding N-channel MOS FET's in the column direction and, similarly to the N-channel MOS FET's, have an arrangement of a drain region, a gate electrode, a source electrode, another gate electrode and another drain region in this order in parallel with the row direction. The P-channel MOS FET's in other basic cells in the same row are disposed side by side. The N- and P-channel MOS FET's are wired with first layer wirings disposed over the N- and P-channel MOS FET's and second layer wirings disposed over the first layer wirings.
Fundamental logic circuits such as an inverter, AND, OR, NAND or NOR are formed with MOS FET's in a basic cell or several adjacent basic cells. Since respective fundamental logic circuits use the N- and P-channel MOS FET's, a number of first and second layer wirings are required to form the logic circuits. This means that, since the wirings between the logic circuits also uses the first and second layer wirings, the complicated wirings in the logic circuits decrease a freedom of wirings between logic circuits.
Another problem is based on power supply wirings which are disposed on N- and P-channel MOS FET's in the direction of the row. The power supply wirings are made of aluminum and formed as the first layer wirings. The first layer wirings cannot be made thick, because, if the first layer wirings are thick, the second layer wirings formed on the first layer wirings via an insulator film to cross the first layer wirings are likely to be broken at edges of the first layer wirings. Furthermore, the power supply wirings cannot be made wide to keep the size of MOS FET thereunder miniature. Therefore, the power supply wirings of the first layer wiring have a small current capacity which easily causes an electromigration.